Through silicon via (TSV) structures have recently been developed as a method to produce three dimensional (3D) electronic integrated devices. These TSV structures entail forming a metal plug inside a small hole in the silicon or other substrate material, wherein the typical hole size may be from about 1 to 30 microns in diameter and from 10 to 250 microns in depth. To fabricate a TSV structure, holes are first etched into the silicon or substrate material, the hole(s) are coated with an insulating material, silicon dioxide for example, which is then covered with a barrier material such as titanium, tantalum, or their nitrides, titanium nitride or tantalum nitride, for example, and the hole is then filled with a conductive material, copper for example. A conventional means of filling the TSV with copper is to use electroplating using one of various means to cause the electroplating to deposit copper preferentially near the bottom of the hole and cause the copper to deposit more inside the via then on the flat surface, or field, of the silicon substrate; this is the well known bottoms-up copper damascene filling electroplating process method. To enable this conventional method it is necessary to form a plating seed layer on which to grow the electroplated film, typically the seed layer is of the same material as the electroplated filling step material, typically both are copper, and the copper plating seed layer is conventionally formed by physical vapor deposition (PVD). A difficulty in conventional methods using PVD metal layers in the case of high aspect ratio TSV structures (compared to damascene structures) is that very little if any of the physical vapor deposited metal coats the interior surfaces of the TSV hole, and therefore an incomplete and inadequate barrier and seed metal layers form in those regions. This disadvantage of PVD increases as the depth to diameter (i.e. aspect) ratio of the TSV increases because of the ballistic transport nature of PVD, this will be discussed in more detail below with reference to prior art.
To achieve the commercial and reliability benefits of three dimensional IC fabrication it is advantageous to fabricate the TSV holes with a high ratio of depth to diameter, aspect ratios of 10 or more are advantageous. Alternate means of conventionally depositing the metal layers into the high aspect ratio TSV feature are atomic layer deposition (ALD) or chemical vapor deposition (CVD). ALD deposits metal films one atomic layer after another through a series of surface limited reactions which are virtually independent of the microscale geometry of surface and hence provides a technically ideal means of coating TSV interior features with metal layers, however the ALD process is slow and therefore commercially too uneconomical for many production TSV applications. CVD is a well known and commercially economical means of depositing TiN, TaN, or W barrier metals into high aspect ratio holes however it has been found to be uneconomical for copper, or other seed layer metals, due to the instability and expense of the metal-organic precursor materials. Conventional wet processes, such as electrochemical deposition (ECD) and electroless metal deposition have also shown to be deficient in commercial fabrication of microscale structures. In the case of electroless metal deposition, a chemical potential may be caused by reaction of the fluid borne reactants and catalytic species on the TSV interior surface. Electroless metal deposition requires a series of chemical pre-treatments in order to set-up the reaction potential between the barrier metal and the seed metal reactants, and the chemical constituents of the pre-treatment and deposition chemical baths must be tightly controlled, all of which can make the electroless metal process expensive and difficult to operate. The alternative conventional wet process method, conventional ECD, suffers from other deficiencies that render it also not production worthy. For example, a significant difficulty of using conventional means for ECD to deposit seed metal on the interior surfaces of TSV features of a substrate coated with highly resistive barrier metal, for example a TiN with resistivity of 10 to 100 ohms/square, is the large radial electrical potential drop that occurs within the barrier metal as current flows from the substrate perimeter to the substrate center, this large potential drop causes an undesirable difference in the available driving electrical potential between edge and center regions of the substrate. Electrical contact to the substrate is formed at the substrate edge and the circuit is completed through the barrier metal and into the electrochemical bath. Consequently a highly resistive metal layer causes a significant voltage drop from edge to center of substrate. A conventional means of overcoming this difficulty of conventional ECD is addressed by Andricacos in U.S. Pat. Pub. No. 2005/0199502, U.S. application Ser. No. 11/123,117, wherein a method of causing the deposition front to proceed from substrate edge to substrate center by using chemical additives to block further deposition on the copper seed metal and thereby causing preferential deposition on the uncovered region of barrier metal while using the deposited copper as an advancing electrical conduction layer. A potential difficulty with this method is controlling the chemical additive concentrations in the appropriate ranges to cause sufficient nucleation potential difference between the barrier metal and the copper metal surfaces. Therefore conventional methods and apparatus have proven inadequate for fabrication of TSV structures.